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FDS3672
February 2002
FDS3672
100V, 0.022 Ohms, 7.5A, N-Channel UltraFET(R) Trench MOSFET
General Description
(R) UltraFET devices combine characteristics that enable benchmark efficiency in power conversion applications. Optimized for Rds(on), low ESR, low total and Miller gate charge, these devices are ideal for high frequency DC to DC converters.
Features
* rDS(ON) = 0.019 (Typ.), VGS = 10V * Qg(TOT) = 28nC (Typ.), VGS = 10V * Low QRR Body Diode * Maximized efficiency at high frequencies * UIS Rated
Applications
* * * * DC/DC converters Telecom and Data-Com Distributed Power Architectures 48-volt I/P Half-Bridge/Full-Bridge 24-volt Forward and Push-Pull topologies
Branding Dash
5
5 1 2 3 4
4 3 2 1
6 7
SO-8
8
MOSFET Maximum Ratings TA=25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TA = 25oC, VGS = 10V, RJA = 50oC/W) Continuous (TA = 100oC, VGS = 10V, RJA = 50oC/W) Pulsed PD TJ, TSTG Power dissipation Derate above 25oC Operating and Storage Temperature 7.5 4.8 Figure 4 2.5 20 -55 to 150 A A A W mW/oC
o
Ratings 100 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case Thermal Resistance Junction to Case at 10 seconds Thermal Resistance Junction to Case at Steady State
(NOTE1) (NOTE2) (NOTE2)
25 50 85
o o o
C/W C/W C/W
Package Marking and Ordering Information
Device Marking FDS3672 Device FDS3672 Reel Size 330mm Tape Width 12mm Quantity 2500units
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 80V VGS = 0V VGS = 20V TC = 150o 100 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 7.5A, VGS = 10V ID = 6.8A, VGS = 6V 2 0.019 0.023 4 0.022 0.028 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgd Qgs2 Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge Gate Charge Threshold to Plateau VDS = 25V, VGS = 0V, f = 1MHz VGS= 0V to 10V VGS = 0V to 2V VDD = 50V ID = 7.5A Ig = 1.0mA 2015 285 70 28 4 10 6.8 6 37 6 pF pF pF nC nC nC nC nC
Resistive Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 4A VGS = 10V, R G = 10 14 20 37 27 51 96 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 7.5A ISD = 4A ISD= 7.5A, dISD /dt =100A/s ISD= 7.5A, dISD /dt =100A/s 1.25 1.0 55 90 V V ns nC
NOTE: 1: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal referance is defined as the solder mounting surface of the drain pins. R JA is guaranteed by design while RCA is determined by the user's board design. 2: RJA is measured with 1.0 in2 copper on FR-4 board.
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Typical Characteristic
1.2 POWER DISSIPATION MULTIPLIER
TA = 25oC Unless Otherwise Noted
8 VGS = 10V
1.0 ID, DRAIN CURRENT (A) 6
0.8
0.6
4
0.4
2
0.2 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC)
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
3 1 THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
ZJA, NORMALIZED
0.1 PDM
t1 0.01 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x R JA + TA 10-2 10-1 10 0 t , RECTANGULAR PULSE DURATION (s) 101 102 103
0.001 10-5
10-4
10-3
Figure 3. Normalized Maximum Transient Thermal Impedance
1000 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
IDM , PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 VGS = 10V
10 5 10-5 10-4 10-3 10-2 10-1 t , PULSE WIDTH (s) 100 101 102 103
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Typical Characteristic (Continued) TA = 25oC Unless Otherwise Noted
30 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) 10 STARTING TJ = 25oC 20 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = 25oC
IAS, AVALANCHE CURRENT (A)
10 TJ = 150 oC TJ = -55oC
STARTING TJ = 150oC 1 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Unclamped Inductive Switching Capability
30 VGS = 10V VGS = 6V VGS = 5V 2.0
Figure 6. Transfer Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE
ID, DRAIN CURRENT (A)
20
1.5
10
VGS = 4.5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
1.0
VGS = 10V, ID = 7.5A 0.5
0 0.0 0.5 1.0 1.5 2.0 VDS , DRAIN TO SOURCE VOLTAGE (V)
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 7. Saturation Characteristics
Figure 8. Normalized Drain To Source On Resistance vs Junction Temperature
1.10
1.4 VGS = VDS, I D = 250A 1.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
ID = 250A
1.05
1.0
1.0
0.8
0.95
0.6
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (o C)
0.90 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature
Figure 10. Normalized Drain To Source Breakdown Voltage vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Typical Characteristic (Continued) TA = 25oC Unless Otherwise Noted
5000 CISS = C GS + CGD VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 50V 8
1000 C, CAPACITANCE (pF)
COSS CGS + C GD
6
CRSS = CGD 100
4 WAVEFORMS IN DESCENDING ORDER: ID = 7.5A ID = 1A 0 5 10 15 20 25 30
2
VGS = 0V, f = 1MHz 10 0.1 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V)
0 Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain To Source Voltage
Figure 12. Gate Charge Waveforms For Constant Gate Current
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG +
BVDSS
VDS VDD VDD
IAS 0.01
0 tAV
Figure 13. Unclamped Energy Test Circuit
VDS
Figure 14. Unclamped Energy Waveforms
VDD Qg(TOT) VDS
L VGS = 10V VGS
+
VDD DUT Ig(REF) 0 Qg(TH)
VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd
Figure 15. Gate Charge Test Circuit
Figure 16. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
R GS
VGS
0
10%
Figure 17. Switching Time Test Circuit
Figure 18. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM AP = ---------------------------DM R J A
utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R J A = 64 + ----------------------------
26 0.23 + Area
(EQ. 2)
(EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 20 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 64 + 26/(0.23+Area)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 19 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually
150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
RJA (oC/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 19. Thermal Resistance vs Mounting Pad Area
ZJA, THERMAL IMPEDANCE (o C/W)
120
90
60
30
0 10-1 10 0 101 t, RECTANGULAR PULSE DURATION (s) 102 103
Figure 20. Thermal Impedance vs Mounting Pad Area
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
PSPICE Electrical Model
.SUBCKT FDS3672 2 1 3 ; CA 12 8 6.0e-10 Cb 15 14 7.4e-10 Cin 6 8 2.0e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 107 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1
LGATE
rev August 2001
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + 6 8 14 13 S2B CB + EDS 5 8 8 22 RVTHRES 14 IT VBAT + S2A 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 MWEAK MMED EBREAK RLDRAIN DBREAK 11 + 17 18 DBODY 5 DRAIN 2
RSLC2
5 51 ESG + EVTEMP RGATE + 9 RLGATE 20 18 22 GATE 1 6 8 -
It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.98e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 4.0e-3 Rgate 9 20 1.4 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 1.3e-2 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1
EGS
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),3))} .MODEL DbodyMOD D (IS=5.0E-11 N=1.13 RS=4.4e-3 TRS1=2.0e-3 TRS2=1.0e-6 + CJO=1.4e-9 M=0.58 TT=4.0e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.38 TRS1=2.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.9e-10 IS=1.0e-30 N=10 M=0.6) .MODEL MstroMOD NMOS (VTO=4.05 KP=90 lambda=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.35 KP=6.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4) .MODEL MweakMOD NMOS (VTO=2.76 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1) .MODEL RbreakMOD RES (TC1=8.5e-4 TC2=-2.5e-6) .MODEL RdrainMOD RES (TC1=1.5e-2 TC2=5.5e-5) .MODEL RSLCMOD RES (TC1=1.0e-3 TC2=1.0e-6) .MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-3.4e-3 TC2=-1.7e-5) .MODEL RvtempMOD RES (TC1=-4.4e-3 TC2=2.2e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2002 Fairchild Semiconductor Corporation
+
FDS3672 Rev. A1, February 2002
FDS3672
SABER Electrical Model
REV August 2001 template FDS3672 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.0e-11,nl=1.13,rs=4.4e-3,trs1=2.0e-3,trs2=1.0e-6,cjo=1.4e-9,m=0.58,tt=4.0e-8,xti=4.2) dp..model dbreakmod = (rs=0.38,trs1=2.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.9e-10,isl=10.0e-30,nl=10,m=0.6) m..model mstrongmod = (type=_n,vto=4.05,kp=90,lambda=0.02,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.35,kp=6.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5) LDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1) DPLCAP 5 DRAIN 2 c.ca n12 n8 = 6.0e-10 10 c.cb n15 n14 = 7.4e-10 RLDRAIN RSLC1 c.cin n6 n8 = 2.0e-9
51
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 107 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.98e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 19.8
S1A 13 8 ESG
RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 50 RDRAIN EVTHRES 16 21 + 19 8 MMED MSTRO 8 DBREAK 11 MWEAK EBREAK + 17 18 -
DBODY
LSOURCE 7 RLSOURCE 18 RVTEMP
SOURCE 3
RSOURCE 12 S2A 14 13 S2B 13 + EGS 6 8 CB + EDS 5 8 8 RVTHRES 14 IT RBREAK 17
15
S1B CA
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.5e-4,tc2=-2.5e-6 res.rdrain n50 n16 = 4e-3, tc1=1.5e-2,tc2=5.5e-5 res.rgate n9 n20 = 1.4 res.rslc1 n5 n51 = 1.0e-6, tc1=1.0e-3,tc2=1.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 1.3e-2, tc1=4e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3.4e-3,tc2=-1.7e-5 res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
19 VBAT + 22
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/110))** 3)) } }
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
FDS3672
SPICE Thermal Model
REV August 2001 FDS3672 Copper Area =1.0 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25
th
JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
SABER Thermal Model
Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =2e-3 ctherm.ctherm2 c2 c3 =5.0e-3 ctherm.ctherm3 c3 c4 =1.0e-2 ctherm.ctherm4 c4 c5 =4.0e-2 ctherm.ctherm5 c5 c6 =9e-2 ctherm.ctherm6 c6 c7 =0.2 ctherm.ctherm7 c7 c8 =1 ctherm.ctherm8 c8 tl =3 rtherm.rtherm1 th c2 =0.1 rtherm.rtherm2 c2 c3 =0.5 rtherm.rtherm3 c3 c4 =1 rtherm.rtherm4 c4 c5 =5 rtherm.rtherm5 c5 c6 =8 rtherm.rtherm6 c6 c7 =12 rtherm.rtherm7 c7 c8 =18 rtherm.rtherm8 c8 tl =25 }
2
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
CASE
TABLE 1. THERMAL MODELS COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25
(c)2002 Fairchild Semiconductor Corporation
FDS3672 Rev. A1, February 2002
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
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This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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